There are many applications where it is desirable to sample the amplitude of a signal at a known point in time and then to perform subsequent processing on that sampled value. Such sampling is frequently performed by connecting a capacitor to an input node which is often a voltage driven node such that the capacitor can be charged to the voltage of the voltage driven node. A switch is generally provided in series with the capacitor so as to break the circuit at a given moment in time thereby trapping charge on the capacitor and consequently holding the voltage that was across that capacitor fixed. In this “hold” state where the switch has been opened it is highly desirable that voltage changes at the input node do not cause perturbations in the voltage that has been held on the capacitor. However, in practice, the switch may be implemented using mechanical or semiconductor components which are imperfect. Imperfections, such as parasitic capacitance, allow fluctuations at the input node to perturb the voltage held on the capacitor. This in turn can cause subsequent processes such as analog to digital conversions to become perturbed and possibly to arrive at incorrect results.